1. Field of the Invention
The present invention relates to a method for controlling a semiconductor manufacturing process, and more particularly to a method for controlling a semiconductor manufacturing process by failure analysis feedback.
2. Description of the Prior Art
Generally, a semiconductor device is manufactured by lots under the same process conditions, and then subjected to an electrical test for each die. Bad dies and good dies are checked and electrically sorted to determine a yield per lot or per wafer. After the semiconductor manufacturing processes for a certain lot are completed, failure analysis is performed to search for a correlation, if any, among the manufacturing processes which influence the final yield.
Referring now to FIG. 1, there is illustrated a failure analysis system in accordance with the prior art. The failure analysis system includes an equipment data base 12 and a yield data base 22. The equipment data base 12 records certain conditions of a semiconductor manufacturing process which was run, including among others, such process conditions as temperature, pressure, vacuum level, and the type and composition of gases used. Such fabrication lot process history data is identified as Step 10 in FIG. 1.
In the yield data base 22, there is recorded a yield per lot, the yield being obtained by checking and sorting bad dies and good dies through electrical testing of each die. Such an electrical die sort (EDS) yield process is identified as Step 20 in FIG. 1.
When checking the yield for each lot through the electrical die sort EDS to form the yield data base 22, an abnormal wafer and the equipment for which a yield decrease has occurred is identified. Defects generated by a specific process condition or abnormal equipment conditions are predicted and sorted (Step 24). Also, a normal wafer or equipment operation is sorted by reference to the equipment data base 12 (Step 14).
The abnormal equipment data and the normal equipment data are merged (Step 30) and compared to each other by analysis of the correlation among the yield, the equipment and the process conditions, the analysis being performed by either or both of a statistical process, such as a significance test, or visual analysis such as graphic processing (Step 40). Then, a unit process equipment, which led to a decrease in the yield, is searched to estimate a failure by checking the equipment conditions and the process conditions (Step 50).
However, in such a conventional failure analysis system, it takes a long time to analyze the failure. Also, even if the failure is rapidly analyzed, the failure analysis is performed on the basis of the run already completed. Although the failure analysis has been accomplished, the wafer manufacturing process still continued under the abnormal process conditions for the subsequent run. As such, the generation of the failure or the yield decrease cannot be prevented during the current, on-line semiconductor process run.